A bookmarks format index of EDA Software websites.

Concurrent engineering strategies and ASIC design methodologies used to develop several large-scale, submicron ASIC products; implemented using multivendor EDA tools running on a heterogeneous network of multiprocessor servers.

There has been a thread about the generation of statistical wireload models in ESNUG 377 and 378 lately, with several good references quoted there. However I have some cautions about depending too heavily on Statistical Wireload Models.

Kevin Hubbard has released ChipVault a lightweight design management tool
for large chip design projects. The ChipVault design organizer provides hierarchical
HDL source file organization, hierarchical viewing, block instantiation,
revision and issue tracking, and hooks for launching EDA tools from the framework.
Written in Perl, the tool is small and efficient. Kevin is currently working on a
Tk GUI port of the tool, and is requesting Alpha testers for the graphical version.

EEDesign Exclusive -
Consultant and ASIC designer Tom Moxon has evaluated deep submicron IC design flows using
open-source cores and new EDA tools. He will report his findings in a five-part article series for EEdesign.
In this initial article, Moxon provides an overview of the emerging deep submicron design flow.
Subsequent articles will provide more details about tools from vendors such as InTime,
Incentia, Icinergy, and Tera Systems.

EEDesign Exclusive -
In this final installment of his 5-part series,
ASIC designer Tom Moxon shows how you can pull IC design flows together
using resource management, dependency graphing tools and the Resource Definition Framework (RDF).